The present invention relates to the fabrication of resistors and interconnect layers, and more particularly to the fabrication of resistor loads and interconnect layers for memory cells.
As is well known in the art, integrated circuits often make use of multiple interconnecting layers. Such arrangements reduce chip area for a given number of devices or circuit elements. Resistors, forming one class of those elements, are often used as load elements in circuits and particularly in static random access memory (SRAM) cells.
Additionally, circuit elements and layers must be electrically connected to one another by way of conductive interconnect lines. Traditionally, these lines have been fabricated by depositing at least one metallization layer. Long connections are ideally formed of materials having very low resistivity, such as aluminum. For local interconnect of nearby elements and interlayer connection, such extremely low resistivity is not critical, though resistivity should not be excessively high.
Polycrystalline silicon, or polysilicon for short, provides fairly good conduction for interconnection over short distances, especially when heavily doped. More importantly, it may be doped with n- or p-type dopants to provide good ohmic (low resistance) contact to similarly doped active areas.
Alternatively, silicide may be used as an interconnect layer. Refractory metal silicides, and especially titanium silicide (TiSi.sub.2), are increasingly used to form interconnects for integrated circuits. Like doped polysilicon, refractory metal silicides form good ohmic contact with silicon, but suicides also have lower sheet resistivity and thus low overall resistivity. Furthermore, silicides can form good ohmic contact, without doping, to both n- and p-type device regions.
One common method of forming metal silicide is a self-aligned silicidation process, often referred to as "salicidation." A thin layer of refractory metal, such as tungsten or titanium, is deposited over a polysilicon layer or other silicon source. For example, titanium metal may be deposited over a dielectric layer and into a contact window formed through the dielectric. The titanium thus contacts an underlying polysilicon layer at the contact window. During a high temperature first sinter step in a nitrogen environment, titanium reacts with the silicon exposed at the contact to form titanium silicide (predominantly TiSi.sub.2). The titanium which overlies the dielectric reacts with ambient nitrogen to form titanium nitride (TiN). After the first sinter, the TiN and unreacted titanium may be removed in a wet etch and a final sinter is performed to lower the silicide's sheet resistance to acceptable levels. The final sinter converts the titanium from the C49 phase to the lower resistance C54 phase.
The multiple layers required to form integrated circuits require several mask steps. Each additional mask which is required entails additional expense and time. For example, fabrication of an SRAM memory cell, including load elements, typically requires at least four layers on top of the substrate: (1) a first polysilicon layer to form transistor gates; (2) a second polysilicon layer for providing local interconnect; (3) a third polysilicon layer to form the resistor; and (4) a metallization layer for forming interconnect with other circuit elements outside the memory array.
Thus, a need exists for a low cost process for forming resistors and interconnect in the same layer, thereby requiring fewer mask steps than past processes have required.